1. Technical Field
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device with reduced testing time.
2. Discussion of the Related Art
Semiconductor memory devices are tested using low frequency memory tests for identifying locations of defective memory cells and high frequency memory tests for determining whether semiconductor memory devices operate correctly.
The low frequency test divides a semiconductor memory array into memory blocks and simultaneously tests the memory blocks to determine whether memory cells are defective. For the low frequency test, a parallel bit test technique may be used where data having the same value are written into the memory cells and data output from the memory cells during a read operation are compared.
The high frequency test checks whether a selected memory cell operates correctly in an actual operation by writing test pattern data having an expected value into the selected memory cell and by checking whether the data output from the selected memory cell has the expected value. However, the number of memory cells which can be simultaneously subjected to a single high frequency test is limited, and thus the same test operation is repetitively performed to check whether all of the memory cells operate correctly.
Thus, the high frequency test time is longer and testing cost is higher than the low frequency test.
FIG. 1 is a circuit diagram of a conventional semiconductor memory device having four (4) data IO pins a 4-bit burst latency. The semiconductor memory device includes a memory cell array divided into four (4) memory blocks MB1 to MB4, a column decoder 1, a row decoder 2, a data IO controller 3, a test control signal generator 4, a data IO portion 5, and an operation controller 6. Each of the memory blocks MB1 to MB4 is divided into four (4) sub blocks SMB1 to SMB4 according to the four (4) data IO pins and a 4-bit burst latency, and each sub block SMB1 to SMB4 simultaneously writes or reads four (4) data D00 to D30, D01 to D31, D02 to D32, and D03 to D33, respectively, according to the 4-bit burst latency. Under control of the column decoder 1 and the row decoder 3, only one memory block MB1 writes or reads data during the high frequency test, and all of the memory blocks MB1 to MB4 simultaneously write or read data during the low frequency test.
The column decoder 1 decodes a column address CA to generate column select signals for selecting one memory block MB1, MB2, MB3, or MB4, when performing the read or write operation during the high frequency test, and to generate a column select signal for simultaneously selecting all of the memory blocks MB1, MB2, MB3, and MB4 during the low frequency test.
The row decoder 2 decodes a row address RA to generate a word line enable signal for selecting one memory block MB1, MB2, MB3, or MB4, when performing the read or write operation during the high frequency test and to generate a word line enable signal for simultaneously selecting all of the memory blocks MB1, MB2, MB3, and MB4 during the low frequency test.
The data IO controller 3 includes four (4) DEMUXs 3_11 to 3_14 which parallel-convert 4 serial test pattern data D00,01,02,03 to D30,31,32,33 into 16 parallel data D00 to D30, D01 to D31, D02 to D32, and D03 to D33 and apply them to the corresponding memory blocks MB1 to MB4 and four (4) MUXs 3_21 to 3_24 which serial-convert 16 parallel data D00 to D30, D01 to D31, D02 to D32, and D03 to D33 into 4 serial test pattern data D00,01,02,03 to D30,31,32,33. During the high frequency test, only one DEMUX 3_11, 3_12, 3_13, or 3_14 or MUX 3_21, 3_22, 3_23, or 3_24 is enabled as in a non-test, normal operation. However, during the write operation of the low frequency test, all DEMUXs 3_11, 3_12, 3_13, and 3_14 are enabled to apply the parallel-converted data D00 to D30, D01 to D31, D02 to D32, and D03 to D33 to all of the memory blocks MB1, MB2, MB3 and MB4, and during the read operation of the low frequency test, all of the MUXs 3_21, 3_22, 3_23, and 3_24 are disabled to avoid outputting data to the data IO portion 5. Therefore, data conflict is averted between error detecting signals err_flag1 to err_flag4, output from the test control signal generator 4, and test pattern data D00,01,02,03 to D30,31,32,33, output from the data IO controller 3.
Here, each of the test pattern data D00,01,02,03 to D30,31,32,33 applied during the low frequency test is 4-bit serial data having the same data value.
The test control signal generator 4 includes comparators 4_1 to 4_4 which respectively correspond to a plurality of memory blocks MB1 to MB4 and compare 16 data D00 to D30, D01 to D31, D02 to D32, and D03 to D33 output from the corresponding memory block MB1, MB2, MB3, or MB4 twice in a sub block (SMB1 to SMB4) unit and a memory block (MB1) unit to generate the error detecting signals err_flag1 to err_flag4 which indicate whether an error occurs during the read operation of the low frequency test.
The data IO portion 5 includes data input portions 5_11 to 5_14 and data output portions 5_21 to 5_24 which are respectively connected to 4 data IO pins (not shown). Each data input portion 5_11, 5_12, 5_13, and 5_14 applies the test pattern data D00,01,02,03 output from the corresponding data IO pin to the DEMUX 3_11, and each data output portion 5_21, 5_22, 5_23, and 5_24 applies the test pattern, data D00,01,02,03 or the error detecting signal err_flag1 to the corresponding data IO pin.
The operation controller 6 determines an operation state of the semiconductor memory device in response to command signals applied from an external portion and generates control signals, such as a DEMUX enable signal dme, a MUX enable signal me, a low frequency test signal Itest, and a high frequency test signal htest, to control operation of the semiconductor memory device. That is, the operation controller 6 has all of the memory blocks MB1 to MB4 write data having the same data value according to the test pattern data D00,01,02,03 to D30,31,32,33 applied from the external portion and then to read them to generate a plurality of error detecting signals err_flag1 to err_flag4 during the low frequency test, and has one memory block MB1, MB2, MB3, or MB4 to write and read data as in a non-test normal operation to generate the test pattern data D00,01,02,03 to D30,31,32,33 during the high frequency test.
In low frequency test mode, the semiconductor memory device receives the 4 test pattern data D00,01,02,03 to D30,31,32,33 having the same data value from the external portion and performs a burst writing operation to store 16 data D00 to D30, D01 to D31, D02 to D32, and D03 to D33 having the same data value in the sub blocks SMB1 to SMB4 in all of the memory blocks MB1 to MB4, respectively. In this state, a burst reading operation is performed to have the sub blocks SMB1 to SMB4 in all of the memory blocks MB1 to MB4 to output the 16 data D00 to D30, D01 to D31, D02 to D32, and D13 to D33, respectively.
The comparators 4_1 to 4_4 respectively compare the 16 data D00 to D30, D01 to D31, D02 to D32, and D03 to D33 output from the memory blocks MB1 to MB4 twice in a sub block (SMB1 to SMB4) unit and a memory block (MB1 to MB4) unit to generate the error detecting signals err_flag1 to err_flag4, and the data output portions 5_21 to 5_24 respectively output the error detecting signals err_flag1 to err_flag4 to the external portion.
An external test device receives and analyzes the error detecting signals err_flag1 to err_flag4. When all of the error detecting signals err_flag1 to err_flag4 have a high logic level all of the memory blocks MB1 to MB4 operate correctly, and when an individual error detecting signal has a low logic level, the memory block corresponding to the individual error detecting signal is defective.
Subsequently, a high frequency test operation of the semiconductor memory device will be explained.
In high frequency test mode, the semiconductor memory device receives the 4 test pattern data D00,01,02,03 to D30,31,32,33 from the external portion and performs a burst writing operation to store 4 data D00 to D30, D01 to D31, D02 to D32, and D03 to D33 in the sub blocks SMB1 to SMB4, respectively, in one memory block MB1, MB2, MB3, or MB4. In this state, a burst reading operation is performed to have the sub blocks SMB1 to SMB4 in one memory block MB1 to output the 16 data D00 to D30, D01 to D31, D02 to D32, and D13 to D33, respectively. At this time, as the test pattern data used for the high frequency test, 4-bit serial data having different data values may be used differently from the low frequency test.
One MUX 3_21 serial-converts the 16 data D00 to D30, D01 to D31, D02 to D32, and D03 to 033 output from one memory block MB1 to generate the 4 test pattern data D00,01,02,03 to D30,31,32,33, and the data IO portion 5 output the 4 test pattern data D00,01,02,03 to D30,31,32,33 to the external portion.
The external test device receives and analyzes the 4 test pattern data D00,01,02,03 to D30,31,32,33 output from the semiconductor memory device and checks whether the 4 test pattern data D00,01,02,03 to D30,31,32,33 are identical to the test pattern data D00,01,02,03 to D30,31,32,33 input to the semiconductor memory device, thereby checking whether the certain memory block MB1 and peripheral circuits for driving it operate correctly.
The high frequency test operation described above is performed again to check whether the other memory block MB2 which is not tested and its peripheral circuits operate correctly. That is, the semiconductor memory device having the 4 memory blocks MB1 to MB4 like FIG. 1 has to be subjected to the same test operation four times to complete the high frequency test.